1. Field of the Invention
The present invention is generally in the field of semiconductors. More particularly, the invention is in the field of ESD protection structures in semiconductor dies.
2. Background Art
“Multi-finger” FETs, such as multi-finger MOSFETs, are used as a major electrostatic discharge (ESD) component in many CMOS applications. In order to discharge ESD current uniformly, a multi-finger FET should be designed such that all portions of the multi-finger FET turn on simultaneously. However, due to process variations and a continual scaling down of device size in advanced technologies, it is difficult for all portions of a multi-finger FET to conduct ESD current uniformly. Thus, a portion of the multi-finger FET may turn on faster than another portion of the multi-finger FET and become “a hot-spot,” which can localize more ESD current. By localizing more ESD current, the hot-spot can cause early ESD failure in the form of filamentation or thermal runaway.
To avoid the creation of a hot-spot in an ESD structure, a ballast resistor has been connected in series with a drain and/or source of the multi-finger FET to assist in uniformly distributing ESD current. In one conventional approach, a salicide block layer is added on the active region between drain contact and gate edge of a multi-finger FET such that an unsalicided active region operates as a local ballast resistor. However, this approach requires a large layout area and introduces a high drain-to-bulk parasitic capacitance, which severely degrades device high frequency performance.
In another conventional approach, a ballast resistor can be formed by connecting an N well resistor in series with a drain of a multi-finger FET. However, the N well resistor also requires a large layout area and undesirably introduces high parasitic N well-to-bulk capacitance to the drain, thereby severely degrading device high frequency performance.
In yet another conventional approach, a number of segmented active strips are used on both drain and source sides of the gate of a multi-finger FET such that each segmented active strip provides an equivalent local ballast resistor. However, in this approach, an increase in ballast resistance requires a corresponding increase in the length of each segmented active strip, which undesirable increases layout area. By increasing the layout area, drain-to-bulk and/or source-to-bulk parasitic capacitance is also increased, which degrades high frequency performance of the device.
Thus, there is a need in the art for an ESD protection structure that provides increased ESD current distribution uniformity without undesirably increasing layout area, and without degrading high frequency performance.